We're a fast growing semiconductor research and IP development company. We provide innovative, word-leading software and hardware that enables ultra-high performance and error resilient signal processing to accelerate future generations of wireless communications.
This is a unique opportunity to join a fast-growing company on the South coast, with international reach. We are looking for a highly capable, enthusiastic and personable individual to join our team. We are specifically seeking a Graduate Engineer; either recently or soon to be graduated with knowledge of the following: C/C++, System Verilog, UVM, Python or Matlab, to contribute to the development of IP, system and board solutions within our product portfolio. This is a hands-on role, which will play an important part in the growth of AccelerComm and its product portfolio.
Contribute and eventually take responsibility for the successful and timely delivery of portions of projects by providing technical capabilities and skills, in RTL design, Software development, implementation and verification
Collaborate with colleagues on the micro-architecture, verification test plan, design, development, verification, SoC physical implementation, FPGA implementation and documentation of our IP
Develop RTL implementations of our IP, using SystemVerilog
Develop Software Implementations of IP, using C/C++ and Matalb
Develop test benches for RTL implementations of electronics systems for communication, using SystemVerilog, SystemC and DPI
Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques and be able to offer improvements to improve efficiency and quality of design and product
Be willing to work in different areas of the AccelerComm development team to expand knowledge across multiple disciplines.
Skills Knowledge and Expertise
- Degree qualified (or equivalent).
- Experience in digital design in one or more of the following areas: Software, ASIC or FPGA
- Experience of some EDA tools for simulation and synthesis (eg. QuestaSim, Synopsys VCS and Verdi, Intel Quartus, Xilinx Vivado)
- Knowledge of an RTL language (VHDL, Verilog, SystemVerilog)
- Knowledge of a scripting language (e.g. Bash, Perl, Python, TCL)
- Knowledge of a Software language (C/C++, Matlab) targeting x86 or Arm
- Technical documentation writing – report writing
- Knowledge of communications signal processing algorithms (ideally error correction, equalisation, channel estimation, beamforming or another baseband component)
- Appreciation of mobile communications systems
- Experience of logic equivalency checking tools – Formality/Conformal
- Understanding of version control systems such as Git, Perforce etc. to enable advanced version control techniques
- Understanding of AXI interfacing (AXI MM, AXILite and AXI Streaming) and understanding of RTL implementation of these interfaces
- Experience of developing code for a ‘home project’ as part of a hobby
- Must be personable, highly capable, motivated, enthusiastic and innovative
- Should have some experience of relevant industry tools, techniques and technology
- Should be a supportive team player, willing to learn from technical leads and senior engineers, open to new ideas and new ways of working
- Should be presentable and with the commitment to build long term viable relationships with all stakeholders
- Good communication skills – written, presentational and verbal
- Have a passion for writing code, mathematics, and engineering.