Principal Design Engineer

Company Details

Description

This is a unique opportunity to join a fast-growing company on the South coast, with international reach. We are looking for a highly capable, enthusiastic and personable individual to join our team. We are specifically seeking a Principal Design Engineer with a broad skillset of relevant industry experience, capable of leading a development of IP and board solutions within our product portfolio. This is a key hands-on role, which will play an important part in the growth of AccelerComm and its product portfolio

Key Responsibilities

  • Provide strategic leadership to inform technical decision-making and planning at a company level
  • Take responsibility for the successful and timely delivery of projects by providing technical leadership and by applying skills and expertise
  • Provide managerial leadership or mentoring to aid the development of junior colleagues and other team members
  • Collaborate with colleagues on the architecture, design, development, verification, SoC physical implementation, FPGA implementation and documentation of our IP
  • Develop RTL implementations of our IP using SystemVerilog
  • Develop test benches for RTL implementations of electronics systems for communication, using SystemVerilog, SystemC and DPI
  • Develop policy and process to enable effective and efficient use of engineering resource
  • Actively contribute to engineering methodology, processes and design techniques to continually improve efficiency and quality of design and product

Skills Knowledge and Expertise
Essential:

  • Degree qualified (or equivalent)
  • Broad experience in delivering digital designs in the ASIC and FPGA industry on modern process nodes and/or FPGA devices
  • Timing and hardware resource optimisation for high throughput data or signal processing applications
  • Expert user of EDA tools for simulation and synthesis (eg. QuestaSim, Synopsys VCS and Verdi, Intel Quartus, Xilinx Vivado, Synopsys DC Ultra, Cadence Genus)
  • Strong understanding of STA and EDA tool and digital design optimisations, to meet timing constraints on both ASIC and FPGA
  • Expert knowledge of an RTL language (VHDL, Verilog, SystemVerilog)
  • Solid knowledge of a scripting language (e.g. Bash, Perl, Python, TCL)
  • Technical documentation writing – design specifications, user guides, verification plans

Desirable:

Knowledge of communications signal processing algorithms (ideally error correction, equalisation, channel estimation, beamforming or another baseband component)

  • Appreciation of mobile communications systems
  • SystemC, Matlab/C/C++ prototyping for design and verification
  • Experience of logic equivalency checking tools – Formality/Conformal
  • Understanding of version control systems such as Git, Perforce etc. to enable advanced version control techniques
  • Familiarity with project management tools (e.g. Jira)
  • Understanding of AXI interfacing (AXI MM, AXILite and AXI Streaming) and understanding of RTL implementation of these interfaces
  • Understanding of telecoms and/or semiconductor industries
  • Experience of maintaining EDA tools (e.g. upgrades, license manager)
  • Experience of creating innovative solutions and documenting them (e.g. in publications or patents)
  • Automation (e.g. Jenkins)
  • Experience using SystemC design modelling and integration

Personal Attributes

  • Must be personable, highly capable, motivated, enthusiastic and innovative
  • Should have hands-on experience of relevant industry tools, techniques and technology
  • Should be a supportive team player and leader, willing to guide others, learn from others, open to new ideas and new ways of working
  • Understands the balance between the need for stability and the need for change in all aspects of the role
  • Should be presentable and with the commitment to build long term viable relationships with all stakeholders
  • Ability to quickly gain customers’ trust
  • Good communication skills – written, presentational and verbal

Tagged as: C++, automation, project management tools

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