New ideas are all around us, but only a few will change the world. That’s our focus at JPL. We ask the biggest questions, then search the universe for answers—literally. We build upon ideas that have guided generations, then share our discoveries to inspire generations to come. Your mission—your opportunity—is to seek out the answers that bring us one step closer. If you’re driven to discover, create, and inspire something that lasts a lifetime and beyond, you’re ready for JPL.

Located in Pasadena, California, JPL has a campus-like environment situated on 177 acres in the foothills of the San Gabriel Mountains and offers a work environment unlike any other: we inspire passion, foster innovation, build collaboration, and reward excellence.

New ideas are all around us, but only a few will alter the world. That’s our focus at JPL. We ask the biggest questions, then search the universe for answers—literally. We build upon ideas that have guided generations, then share our discoveries to inspire generations to come. Your mission—your opportunity—is to seek out the answers that bring us one step closer. If you’re driven to discover, build, and inspire something that lasts a lifetime and beyond, you’re ready for JPL.

Located in Pasadena, California, JPL has a campus-like environment situated on 177 acres in the foothills of the San Gabriel Mountains and offers a work environment unlike any other: we inspire passion, cultivate innovation, build collaboration, and reward excellence.

This outstanding opportunity is part of the Autonomous Systems Division’s Flight Electronics Section which crafted the electronics for the latest Mars rover and helicopter (Perseverance & Ingenuity). Come join a team that proved flying on Mars is possible.

As a senior level FPGA Design Engineer, you will lead the planning and execution of highly sophisticated and unique electronics systems with Laboratory wide impact. Specific responsibilities include:

• Improve FPGA design and verification flow
• Improve hardware resilience techniques
• Apply digital design knowledge and principles to complex designs
• Mentor junior engineers

This position requires the following qualifications:

• Bachelor’s degree in Electronics, Electrical, or Computer Engineering or related discipline with typically a minimum of 6 years of related experience; Master’s in similar disciplines with a minimum of 4 years of related experience; or PhD in similar disciplines with a minimum of 2 years of related experience
• Experience architecting, designing, implementing, and testing advanced digital systems
• Experience crafting FPGAs and embedded processors designs using tools: Synplify Pro/Premier, Xilinx Vivado, Microsemi Libero SoC, and Mentor Graphics Questa design suite
• Some experience leading teams, presenting in design reviews and quarterly management reviews
• Successful supporting FPGA designs through full life cycle from initial concept to burn review.
• Advocate for new design/verification technologies and methodologies
• Experience on fast pace and dynamic product development environment
• Good written/verbal communication skills

Preferred Qualifications:

• Experience designing with radiation tolerant Xilinx and Microsemi FPGAs
• Experience in bus standards protocol such as: sRIO, SpaceWire, PCI, MILSTD-1553, CAN, and Ethernet
• Embedded Software knowledge and experience
• SystemC or C++, Matlab
• Experience with digital twin modeling
• Familiar with Failure Analysis and worst-case analysis

JPL has a catalog of benefits and perks that span from the traditional to the unique. This includes a variety of health, dental, vision, wellbeing, and retirement plans, paid time off, learning, rideshare, childcare, flexible schedule, parental leave and many more. Our focus is on work-life balance, and living healthy, fulfilling lives as we Dare Mighty Things Together. For benefits eligible positions, benefits are effective the first day of the month coincident with or immediately following the employee’s start date.

For further benefits information click Benefits and Perks

The hiring range displayed below is specifically for those who will work in or reside in the location listed. In extending an offer, Jet Propulsion Laboratory considers factors including, but not limited to, the candidate’s job related skills, experience, knowledge, and relevant education/training. Hiring range for this job may be adjusted based on primary work location outside of Pasadena, California. This adjusted range will be provided to candidates by the Recruiter when applicable.

The typical full time equivalent annual hiring range for this job in Pasadena, California.

$112,840 – $148,512

JPL is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to sex, race, color, religion, national origin, citizenship, ancestry, age, marital status, physical or mental disability, medical condition, genetic information, pregnancy or perceived pregnancy, gender, gender identity, gender expression, sexual orientation, protected military or veteran status or any other characteristic or condition protected by Federal, state or local law.

In addition, JPL is a VEVRAA Federal Contractor.

EEO is the Law.

EEO is the Law Supplement

Pay Transparency Nondiscrimination Provision

The Jet Propulsion Laboratory is a federal facility. Due to rules imposed by NASA, JPL will not accept applications from citizens of designated countries or those born in a designated country unless they are Legal Permanent Residents of the U.S or have other protected status under 8 U.S.C. 1324b(a)(3). The Designated Countries List is available here.

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Tagged as: si verification tools, pcb design, Altium tools, fpga based designs