New ideas are all around us, but only a few will change the world. That’s our focus at JPL. We ask the biggest questions, then search the universe for answers—literally. We build upon ideas that have guided generations, then share our discoveries to inspire generations to come. Your mission—your opportunity—is to seek out the answers that bring us one step closer. If you’re driven to discover, create, and inspire something that lasts a lifetime and beyond, you’re ready for JPL.

Located in Pasadena, California, JPL has a campus-like environment situated on 177 acres in the foothills of the San Gabriel Mountains and offers a work environment unlike any other: we inspire passion, foster innovation, build collaboration, and reward excellence.

We are looking for someone with the drive, creativity, and know-how to map the future of flight electronics for deep space probes, planetary rovers and helicopters, segmented robotics, smallsats, and nanosats.  JPL is venturing into the cosmos with platforms that require unprecedented capabilities in autonomy and data processing.

As an Avionics Hardware Architect for JPL’s Autonomous Systems Division’s Flight Electronics Section which crafted the electronics for Europa Clipper and Psyche, the latest Mars rover and helicopter (Perseverance & Ingenuity), your primary responsibility will be to provide systems architecture framing and leadership for development and sustainment of electronic hardware product lines that will perform command and data handling (C&DH) and mechanism control, providing the processors and peripherals to support and host flight software, sensors, scientific payloads, and end effectors on the most ambitious space exploration projects of the coming decades.  Our search for intelligence starts here.

Tasks may include but not limited to:

• Lead development of the next generation of highly complex and unique system architectures for flight electronic product lines across a diversity of space exploration platforms.
  • Command and data handling (C&DH)
  • Motion control
  • Visual landing and navigation
  • Telemetry collection unit
  • Plug-and-play gate array modules
• Serve as a key member of space mission analysis and associated product development initiatives, define appropriate benchmarks for communicating candidate product comparisons, and create and track technology roadmaps.
• Perform hardware-software partitioning, define system data routing and bus structures, functional architectures tolerant of faults and single-event effects (SEE) to drive subsystem (L4) design descriptions, requirements, and interfaces.
• Define plug-and-play architectures that shape and partition development of unit-level (L5), board (L6), and gate array (L7/L8) requirements and interfaces that are reusable and scalable.
• Determine and develop appropriate simulations, analyses, and trade studies, direct studies and approve results.  Validate requirements and designs through modeling and simulation to reduce risk ahead of build commitments.
• Establish and track technical performance measures throughout development cycle for: gate arrays, data buses, processors, memory, critical timing, etc.
• Represent JPL through frequent interface with representatives of organizations outside JPL.   Form and lead multidisciplinary, cross-organizational teams inside and outside JPL.  These teams typically address crucial, complex issues.
• Advise and consult with senior management on advanced and unique issues within and outside own organization.

Qualifications:

• Bachelors in an engineering or appropriate science discipline, with 12+ years of related experience, Masters with 10+ years of related experience or PhD with 8+ years of related experience.
• Deep understanding of applicable industry and/or academic state of the practice and state of the art in two or more of the following: embedded systems; processors; programmable gate arrays; memories.
• Proven track record with development and delivery of digital and/or computer hardware.
• Excellent communications skills, ability to work in interdisciplinary teams, and meet deadlines.

Preferred Skills:

• Familiarity with single board computer and/or peripheral designs for space applications
• Familiarity with the latest industry systems engineering practices
• Familiarity with high-level synthesis methods and tools for hardware design languages and real-time software engineering
• Strong modeling and analysis for digital hardware, processor throughput, data bus sizing and/or traffic analysis, etc.
• Ties into academia/industry, research

JPL has a catalog of benefits and perks that span from the traditional to the unique. This includes a variety of health, dental, vision, wellbeing, and retirement plans, paid time off, learning, rideshare, childcare, flexible schedule, parental leave and many more. Our focus is on work-life balance, and living healthy, fulfilling lives as we Dare Mighty Things Together. For benefits eligible positions, benefits are effective the first day of the month coincident with or immediately following the employee’s start date.

For further benefits information click Benefits and Perks

The hiring range displayed below is specifically for those who will work in or reside in the location listed. In extending an offer, Jet Propulsion Laboratory considers factors including, but not limited to, the candidate’s job related skills, experience, knowledge, and relevant education/training. Hiring range for this job may be adjusted based on primary work location outside of Pasadena, California. This adjusted range will be provided to candidates by the Recruiter when applicable.

The typical full time equivalent annual hiring range for this job in Pasadena, California.

$177,944 – $227,656

JPL is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to sex, race, color, religion, national origin, citizenship, ancestry, age, marital status, physical or mental disability, medical condition, genetic information, pregnancy or perceived pregnancy, gender, gender identity, gender expression, sexual orientation, protected military or veteran status or any other characteristic or condition protected by Federal, state or local law.

In addition, JPL is a VEVRAA Federal Contractor.

EEO is the Law.

EEO is the Law Supplement

Pay Transparency Nondiscrimination Provision

The Jet Propulsion Laboratory is a federal facility. Due to rules imposed by NASA, JPL will not accept applications from citizens of designated countries or those born in a designated country unless they are Legal Permanent Residents of the U.S or have other protected status under 8 U.S.C. 1324b(a)(3). The Designated Countries List is available here.

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Tagged as: Command and data handling, Visual landing and navigation, flight electronic product lines