FPGA Verification Engineer

Company Details

We plan to save a billion people an hour a day

We are looking FPGA/ASIC Verification Engineer preferably with (UVM) skills to join our small team that

is responsible for helping to bring the dream of Urban Air Mobility to market. They will work with the Joby FPGA Team to verify FPGA design functionality in preparation to the FAA Certification process for Airborne Electronic Hardware.

Responsibilities

You will be responsible for writing test plans from module description documents and for writing test benches that implement the test plans. You will work closely with the FPGA engineers during the planning, requirements, design, test and integration phases.

The successful candidate will assist the team in:

  • Design, develop and maintain UVM testbenches
  • Create and review test plan documents
  • Contribute to requirements specifications
  • Participate in module and system-level design reviews

Required

  • B.S. in Computer Science, Electrical Engineering or related field and 3 years of practical experience or
  • MS + 1 year experience.
  • RTL Verification Experience
  • Knowledge of Verilog/SystemVerilog
  • Familiarity with development in a Linux environment
  • Willingness and ability to learn new tools and methodologies

Desired

  • Experience with one or more scripting languages such as Tcl, Python, or Perl
  • Experience with object-oriented programming
  • Experience with FPGAs and FPGA tools, preferably Xilinx Vivado
  • Experience with UVM
  • Experience with DO-254
  • Experience with test-driven design

Tagged as: python, verilog, perl, TCL, systemverilog, xilinx vivado, UVM

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