We are on a mission to build the Internet in Space
Kepler is on a Mission to bring the internet to space. Incorporated in 2015, Kepler’s guiding star is to enable the space economy through the creation of a communication network in Low Earth Orbit (LEO) that will provide connectivity services to other space missions, be they on orbit in LEO, MEO, GEO, or beyond. With an expanding base of early customers and our first 19 satellites in orbit, Kepler is continuing to grow and expand its most important asset – the Team! Based out of our HQ in Toronto and with an office in the UK and a newly formed office in the US we are building towards a truly global company delivering a product for the whole world.
We’re on the hunt for a top-tier FPGA Digital Design Engineer to develop the next generation of our satellites.
At Kepler, you’ll have the opportunity to work with a small dedicated team of engineers building the Kepler spacecraft. You will be responsible for the design and implementation of FPGA code either with a focus on DSP algorithms to modulate and demodulate signals on board our software defined radio (SDR), or embedded systems interfacing with processors and peripherals. To be effective you will need to participate in all phases of FPGA design flow (Simulation, Synthesis, Place & Route, Timing Closure and Hardware Testing). A good understanding of the intricacies of FPGA development would make a candidate standout.
- Develop custom IP for new features of the Kepler SDR and digital payload
- Iterate on current DSP and interface designs to improve reliability
- Work with IP core vendors to integrate new functionality into the Kepler SDR
- Work with lead engineers in developing the communications and network architecture of our future satellite constellation
- Participate in conceptual design studies of new spacecraft
- Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent
- 2+ yr. working experience with Verilog, SystemVerilog, or VHDL
- Solid understanding of timing principles, including clock domain crossing and timing closure
- Strong scripting skills (e.g Python, Tcl, csh/bash, etc.)
- Experience with FPGA tools (e.g Vivado, Quartus), HDL Simulation Tools (ModelSim)
- Masters of Science in Computer/Electrical Engineering, or equivalent
- Experience in coherent digital demodulation of waveforms such as BPSK, QPSK, QAM
- Experience with memory mapped interfaces such as AXI, Wishbone, Avalon
- Experience with high-speed transceivers for protocols such as JESD204B, PCIe, SATA
- Experience designing printed circuit boards
- Knowledge of radio-frequency electronics design