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Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.
The Wireless Solutions Group (WSG) is seeking a Senior Engineer with Design for Test (DFT) expertise to support SOC development for our next generation, mixed signal, wireless products. The role will include driving and optimizing SCAN & MBIST insertion at synthesis, its power optimization, static timing analysis, and verification using an industry leading ASIC design flow. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments.
- Candidate will provide hands on technical work to the WSG Silicon Development Team in the area of design DFT implementation.
- Work with RTL and physical design teams to create SCAN & MBIST inserted netlists on wireless integrated IC products
- Use industry standard tools to generate high coverage ATPG patterns utilizing scan compression
- Build verification environment to run and debug gate level simulations at the SoC level
- Document scan designs and maintain guidelines for best scan design practices
- Define, develop, and improve scan design process flows and methodologies for continuous improvement
- Run, debug, and perform diagnostics on scan patterns post-silicon on a production and/or debug tester
- Ability to set priorities and handle the tasks independently
- Participate in SoC development planning and scheduling.
- Assist in the validation and debug silicon products in support of release to production.
- Sound knowledge of Scan Stitching, Scan Compression, MBIST & JTAG Techniques
- Should have good post silicon DFT bring-up and debug experience
- Should have a good knowledge in simulation debug and prior experience at SoC level
- Knowledgeable in Chip level Design and Integration activities
- Must have 4+ years of experience with Multi Vendor DFT tools such as FastScan and/or TetraMAX
- Must be able to modify Verilog/VHDL
- Must have scripting and automation skills – Linux shell scripting, Perl, Tcl, Makefile, and revision management (CVS, git, etc.)
- Knowledge of stuck-at, transition, IDDQ, and other advanced fault models
- Experience with IJTAG, Boundary Scan, and printed circuit board design desired but not required
- Willing to travel, including internationally (< 5%)
- Excellent debug skills in both functional and gate level simulations
- Self-motivated, able to work independently, excellent communication skills, excellent presentation skills for design reviews, and ability to excel in a multi-national team environment
- Participate in Library and Memory IP selection (benchmarking/evaluations), characterization, and configuration.
- Interface with applications, product and test engineering, development systems, technology development, CAD, layout and other design organizations
- Knowledge and exposure to complete SOC RTL to GDS to silicon release flow is desired
- Knowledge of revision control tools such as CVS, Perforce, Git