GPU Memory Subsystem DV Engineer

Company Details

Our technology has no boundaries! NVIDIA is building the world’s most groundbreaking and state of the art compute platforms for the world to use. It’s because of our work that scientists, researchers and engineers can advance their ideas. At its core, our visual computing technology not only enables an amazing computing experience, it is energy efficient! We pioneered a supercharged form of computing loved by the most demanding computer users in the world - scientists, designers, artists, and gamers. It’s not just technology though! It is our people, some of the brightest in the world, and our company culture make.

Job Description

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

At NVIDIA, our employees are passionate about parallel and visual computing. We’re united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”

What you’ll be doing:

  • Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.
  • You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
  • You will come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.
  • Responsible for performance and deadlock verification of the GPU memory subsystem unit.
  • Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  • Perform functional coverage driven verification closure.
  • You will be working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

What we need to see:

  • B.Tech./ M.Tech. with 2+ years of relevant experience
  • Experience in verification of complex IPs/units and sub-systems
  • Bakground in verification using random stimulus along with functional coverage and assertion-based verification methodologies
  • Expertise in Verilog
  • Knowledge in SystemVerilog or similar HVL
  • Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug

Ways to stand out from the crowd:

  • Experience in memory subsystem or network interconnect IP verification
  • Good debugging and analytical skills
  • Scripting knowledge (Python/Perl/shell)
  • Good communication skills & dream to work as a great teammate

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

 

Tagged as: verilog, python/perl/shell, systemverilog, verification methodologies, HVL, uvm/vmm, memory subsystem, debugging/analytical skills

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