FPGA developer in signal processing for Navigation equipment

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Within the FPGA Business Pole integrated into the Electronics entity, the candidate will be responsible for designing on FPGA technological building blocks for signal processing for RF (BPSQ/QPSK modulation, Correlators, FFT, integrators) meeting the functional needs of the Navigation product line.

The main missions:

  • Participate in the development of the FPGA architecture,
  • Specify the different functional blocks involved in the architecture,
  • Specify the different verification strategies (virtual and on target)
  • Code and simulate the different functional blocks
  • Carry out the various tests at the terminals of the FPGA on an electronic card
  • Participate in the various internal and external reviews with the client (DO 254 certification audit possible)
  • Provide reporting to the batch manager on the progress of activities
  • Provide technical support to the various related business teams (Software/Electronics/System)

Job Requirements

Electronic engineer with a first experience (internship included) the candidate will have to demonstrate:

  • A certain autonomy and knowledge of the following phases: validation of requirements, feasibility of implementation, estimation of resources, design, verification, configuration management
  • Knowledge of HDL description languages ​​(preferably Verilog or systemVerilog). The implementation of advanced methods in verification is a plus (functional coverage by covergroup or assertion, UVM methodology for example).
  • Knowledge of STA constraints
  • Knowledge of simulation (Questa), synthesis/P&R (Synplify Pro, Libero, Vivado) and configuration management (Git) tools.
  • Knowledge of advanced techniques for performing on-target verification is a plus (low-level embedded software on FPGA to run test routines for example)

Transversal skills / soft skills:

  • Organized and rigorous
  • Autonomous
  • Good interpersonal skills, good communication

Tagged as: vivado, synplify pro, libero, FPGA, verilog

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